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128MB, 256MB SODIMM
DDR SDRAM
DDR SDRAM SODIMM
200pin Unbuffered SODIMM based on 256Mb F-die 64 / 72-bit (Non ECC / ECC)
Revision 1.2 March, 2004
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Revision History
Revision 1.0 (June, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. Revision 1.2 (March, 2004) - Corrected package dimension.
DDR SDRAM
Rev. 1.2 March 2004
128MB, 256MB SODIMM
200Pin Non ECC / ECC SODIMM based on 256Mb F-die(x16)
Ordering Information
Part Number M470L1624FT0-C(L)B3/A2/B0 M470L3224FT0-C(L)B3/A2/B0 M485L1624FT0-C(L)B3/A2/B0 Density 128MB 256MB 128MB Organization 16M x 64 32M x 64 16M x 72
DDR SDRAM
Component Composition 16Mx16 (K4H561638F) * 4EA 16Mx16 (K4H561638F) * 8EA 16Mx16 (K4H561638F) * 5EA
Height 1,250mil 1,250mil 1,250mil
Operating Frequencies
B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
Feature
* Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1250 (mil), single(128MB), double(256MB) sided component
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Pin Configurations (Front side/back side)
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65
DDR SDRAM
Pin
135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
Front
VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS
Pin
67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
Front
DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 /CK2 VDD CKE1 DU A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 *DU(A13) VSS DQ32 DQ33 VDD DQS4
Front
DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66
Back
VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS
Pin
68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134
Back
DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 *DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4
Pin
136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
Back
DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
KEY
DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26
KEY
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30
Note 1. * : These pins are not used in this module. 2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64 module, & used on x72 module. Pin 95,122 are NC for 1Row module (M470L1624FT0, M485L1624FT0) & used for 2Row module (M470L3224FT0).
Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0~CKE1 CS0~CS1 RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name DM0 ~ DM7, DM8(for ECC) VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Function Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Serial data I/O Serial clock Address in EEPROM No connection
Rev. 1.2 March 2004
128MB, 256MB SODIMM
DDR SDRAM
128MB, 16M x 64 Non ECC Module (M470L1624FT0) (Populated as 1 bank of x16 DDR SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
CS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS
DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D0
D2
DQS1 DM1
DQS5 DM5
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ58 DQ60 DQ61 DQ62 DQ63
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D1
D3
DQS3 DM3
DQS7 DM7
BA0 - BA1 A0 - A12 RAS CAS CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D3 A0-A12: DDR SDRAMs D0 - D3 RAS: SDRAMs D0 - D3
Cap/Cap/Cap D0/D2/Cap
CAS: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 Clock Input CK0/CK0 CK1/CK1 CK2/CK2
Clock Wiring SDRAMs 2 SDRAMs 2 SDRAMs NC
CK0/1/2 CK0/1/2 Card Edge
R=120 5%
D1/D3/Cap
VDDSPD VDD/VDDQ
Cap/Cap/Cap
SPD D0 - D3 D0 - D3 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2
VREF VSS
D0 - D3 D0 - D3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must SDA be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
DDR SDRAM
256MB, 32M x 64 Non ECC Module (M470L3224FT0) (Populated as 2 bank of x16 DDR SDRAM Module) Functional Block Diagram
CS1 CS0 DQS0 DM0 LDQS LDM CS LDQS CS LDM DQS4 DM4 LDQS LDM CS LDQS CS LDM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
DQS1 DM1
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D0
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
DQS5 DM5
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D2
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D6
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
DQS2 DM2
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
LDQS LDM CS
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
LDQS CS LDM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
DQS6 DM6
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
LDQS LDM CS
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
LDQS CS LDM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
DQS3 DM3
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D1
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
DQS7 DM7
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D3
I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6
UDQS UDM
D7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14
*Clock Net Wiring
D0/D2/Cap
BA0 - BA1 A0 - A12 RAS CAS CKE0 CKE1 WE VDDSPD VDD/VDDQ
BA0-BA1: DDR SDRAMs D0 - D7 A0-A12: DDR SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D3 CKE: SDRAMs D4 - D7 WE: SDRAMs D0 - D7 SPD D0 - D7 SCL WP SDA A0 SA0 A1 SA1 A2 SA2 Serial PD Clock Input CK0/CK0 CK1/CK1 CK2/CK2 Clock Wiring SDRAMs 4 SDRAMs 4 SDRAMs NC CK0/1/2 CK0/1/2 Card
Edge R=120
D1/D3/Cap
D4/D6/Cap D5/D7/Cap
VREF VSS
D0 - D7 D0 - D7
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
DDR SDRAM
128MB, 16M x 72 ECC Module (M485L1624FT0) (Populated as 1 bank of x16 DDR SDRAM Module) Functional Block Diagram
CS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS
DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
DQS8 DM8
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D0
D2
D4
DQS1 DM1
DQS5 DM5
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ58 DQ60 DQ61 DQ62 DQ63
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS
D1
D3
DQS3 DM3
DQS7 DM7
BA0 - BA1 A0 - A12 RAS CAS CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D4 A0-A12: DDR SDRAMs D0 - D4 RAS: SDRAMs D0 - D4 CAS: SDRAMs D0 - D4 CKE: SDRAMs D0 - D4 WE: SDRAMs D0 - D4 Clock Input CK0/CK0 CK1/CK1 CK2/CK2 Clock Wiring SDRAMs 2 SDRAMs 2 SDRAMs 1 SDRAMs
CK0/1/2 CK0/1/2 Card Edge D1/D3/Cap R=120 5% D0/D2/D4 Cap/Cap/Cap
VDDSPD VDD/VDDQ
SPD D0 - D4 D0 - D4 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
Cap/Cap/Cap
VREF VSS
D0 - D4 D0 - D4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 * # of component 50
DDR SDRAM
Unit V V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH
Min
2.3 2.3 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9
Max
2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5
Unit
V V V V V V V uA uA mA mA mA
Note
5 5 1 2
3 4
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
DDR SDRAM
M470L1624FT0 (16M x 64, 128MB Module)
(VDD=2.7V, T = 10C)
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 360 500 12 100 80 140 220 800 760 720 12 6 1,400 A2(DDR266@CL=2) 320 460 12 80 72 120 180 680 620 660 12 6 1,200 B0(DDR266@CL=2.5) 320 460 12 80 72 120 180 680 620 660 12 6 1,200 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M470L3224FT0 (32M x 64, 256MB Module)
(VDD=2.7V, T = 10C)
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 580 720 24 200 160 280 440 1,020 980 940 24 12 1,620 A2(DDR266@CL=2) 500 640 24 160 144 240 360 860 800 840 24 12 1,380 B0(DDR266@CL=2.5) 500 640 24 160 144 240 360 860 800 840 24 12 1,380 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
M485L1624FT0 (16M x 72, 128MB Module)
DDR SDRAM
(VDD=2.7V, T = 10C)
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 810 1,035 27 225 180 315 495 1,260 1,440 1,530 27 14 2,340 A2(DDR266@CL=2) 720 900 27 180 162 270 405 1,080 1,215 1,440 27 14 2,160 B0(DDR266@CL=2.5) 720 900 27 180 162 270 405 1,080 1,215 1,440 27 14 2,160 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 Max
DDR SDRAM
Unit V VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 V V V Note 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0, CKE1) Input capacitance( CS0, CS1) Input capacitance( CLK0, CLK1,CLK2) Input capacitance(DM0~DM7,DM8(for ECC)) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2
(VDD=2.5V, VDDQ=2.5V, TA= 25C, f=1MHz)
M470L1624FT0
Min 41 34 34 25 6 6 Max 45 38 38 30 7 7 -
M470L3224FT0
Min 49 42 42 25 6 6 Max 57 50 50 30 7 7 -
M485L1624FT0
Min 41 34 34 25 6 6 6 Max 45 38 38 30 7 7 7
Unit pF pF pF pF pF pF pF
Rev. 1.2 March 2004
128MB, 256MB SODIMM
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK CL=2.0 CL=2.5
DDR SDRAM
B3 (DDR333@CL=2.5)) Min Max
60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 +0.7 -0.7 +0.7 -0.75 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ
A2 (DDR266@CL=2.0) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
B0 (DDR266@CL=2.5)) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 +0.75 -0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
Unit
ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns
Note
Max
Max
12
3
i,5.7~9 i,5.7~9 i, 6~9 i, 6~9 1 1
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Parameter
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time
DDR SDRAM
B3 (DDR333@CL=2.5)) Min Max
12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.55 0.4 18 (tWR/tCK) + (tRP/tCK) 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin
Symbol
tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP
A2 (DDR266@CL=2.0) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 0.75 0.6
B0 (DDR266@CL=2.5)) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
Unit
ns ns ns ns ns ns ns tCK us ns ns ns tCK
Note
Max
Max
j, k j, k 8 8
4 11 10, 11 11 2
tDAL
tCK
13
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333 & DDR266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Units V/ns Notes a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes i i i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes k k k
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps ps Notes j j j
DDR SDRAM
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Notes e,m
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Component Notes
DDR SDRAM
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 5. For command/address input slew rate 1.0 V/ns 6. For command/address input slew rate 0.5 V/ns and < 1.0 V/ns 7. For CK & CK slew rate 1.0 V/ns 8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 9. Slew Rate is measured between VOH(ac) and VOL(ac). 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 11. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 12. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 13. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
Rev. 1.2 March 2004
128MB, 256MB SODIMM
System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
DDR SDRAM
Test point
Output 50 VSSQ Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ 50 Output Test point Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V, typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V, slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotoy.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1
DDR SDRAM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11, A12 Note
H H H
X X H L H X X
L L L L H L L
L L L H X L H
L L L H X H L
L L H H X H H V V
OP CODE OP CODE X
1, 2 1, 2 3 3 3 3
L H H
X Row Address L H L H X V X L H X
Column Address
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4 4 4, 6 7
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
V
Column Address
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Physical Dimensions : 16M x64 (M470L1624FT0)
DDR SDRAM
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full R 2x
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
2 40 42
0.17 (4.20) 0.096 (2.40)
Z
1.896 (47.40)
2- 0.07 (1.80)
Y
200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102 Min
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 16Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H561638F-T***
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Physical Dimensions : 32M x64 (M470L3224FT0)
DDR SDRAM
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full R 2x
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
2 40 42
0.17 (4.20) 0.096 (2.40)
Z
1.896 (47.40)
2- 0.07 (1.80)
Y
200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102 Min
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 16Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H561638F-T***
Rev. 1.2 March 2004
128MB, 256MB SODIMM
Physical Dimensions : 16M x72 (M485L1624FT0)
DDR SDRAM
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full R 2x
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
2 40 42
0.17 (4.20) 0.096 (2.40)
Z
1.896 (47.40)
2- 0.07 (1.80)
Y
200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102 Min
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 16Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H561638F-T***
Rev. 1.2 March 2004

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